The 9th International Workshop on
Advances in Parallel Programming Models and Frameworks for the Multi-/Many-core Era
CALL FOR PAPERS & PARTICIPATION
Submissions could be for full papers, short papers, poster papers, or posters
You are invited to submit original and unpublished research works on above and other topics related to Many-core computing, modeling and algorithms. Submitted papers must not have been published or simultaneously submitted elsewhere until it appears in HPCS proceedings, in the case of acceptance, or notified otherwise. Submission can be for
- Regular papers, please submit a PDF copy of your full manuscript, not to exceed 8 double-column formatted pages per template, and include up to 6 keywords and an abstract of no more than 400 words. Additional pages will be charged additional fee. Submission should include a cover page with authors' names, affiliation addresses, fax numbers, phone numbers, and all authors email addresses. Please, indicate clearly the corresponding author(s) although all authors are equally responsible for the manuscript.
- Short papers (up to 4 pages), please submit a PDF copy of your full manuscript, not to exceed 4 double-column formatted pages per template, and include up to 6 keywords and an abstract of no more than 400 words. Additional pages will be charged additional fee. Submission should include a cover page with authors' names, affiliation addresses, fax numbers, phone numbers, and all authors email addresses. Please, indicate clearly the corresponding author(s) although all authors are equally responsible for the manuscript.
- Poster papers and Posters (please refer to http://hpcs2020.cisedu.info/1-call-for-papers-and-participation/call-for-posters for posters submission details) will also be considered.
Please specify the type of submission you have. Please include page numbers on all preliminary submissions to make it easier for reviewers to provide helpful comments.
Submit a PDF copy of your full manuscript to the Workshop's paper submission site at xxx. Acknowledgement will be sent within 48 hours of submission.
Only PDF files will be accepted, uploaded to the submission link above. Each paper will receive a minimum of three reviews. Papers will be selected based on their originality, relevance, significance, technical clarity and soundness, presentation, language, and references. Submission implies the willingness of at least one of the authors to register and present the paper, if accepted. At least one of the authors of each accepted paper will have to register and attend (virtually) the HPCS 2020 conference to present the paper at the Symposium as scheduled. By submitting the paper to the HPCS conference, all authors agree to abide by all HPCS conference paper submission, publication and presentation policies as well as following ethical and professional codes of conduct, including those of the professional co-sponsoring organizations. For more information, please refer to the Authors Info and Registration Info pages.
Accepted papers will be published in the Conference proceedings. Instructions for final manuscript format and requirements will be posted on the HPCS 2020 Conference web site. It is our intent to have the proceedings formally published in hard and soft copies and be available at the time of the conference. The proceedings is projected to be included in the IEEE or ACM Digital Library and indexed in all major indexing services accordingly.
Plans are underway to have the best papers, in extended version, selected for possible publication in a reputable journal as special issue. Detailed information will soon be announced and will be made available on the conference website.
If you have any questions about paper submission or the Workshop, please contact the Workshop's organizers.
Paper Submissions: ------------------------------------------- 25 September 2020
Acceptance Notification: -------------------------------------- 09 October 2020
Camera Ready Papers and Registration Due by: ----------- 16 October 2020
Conference Dates: --------------------------------------------- 25 - 29 January 2021
International Program Committee*:
All submitted papers will be rigorously reviewed by the Workshop's technical program committee members following similar criteria used in HPCS 2020 and will be published as part of the HPCS 2020 Proceedings.
(* Committee formation is pending and will be finalized shortly.)
For information or questions about Conference's paper submission, tutorials, posters, workshops, special sessions, exhibits, demos, panels and forums organization, doctoral colloquium, and any other information about the conference location, registration, paper formatting, etc., please consult the Conference’s web site at URL: http://hpcs2020.cisedu.info/ or http://conf.cisedu.info/rp/hpcs20 or contact one of the Conference's organizers.
SCOPE AND OBJECTIVES
With multi- and many-core based systems, performance increase on the microprocessor side will continue according to Moore's Law, at least in the near future. However, as the number of cores and the complexity of on-chip memory hierarchies increases, performance limitations due to slow memory access are expected to get worse, making it hard for users to fully exploit the theoretically available performance. In addition, the increasingly sophisticated design of compute clusters, based on the use of accelerator components (GPGPUs by AMD and NVIDIA, Intel Xeon Phi, integrated GPUs etc.) add further challenges to achieving efficient programming of many-core-based HPC and high-end embedded systems.
Therefore, compute and data intensive tasks can only benefit from the hardware's full potential, if both processor and architecture features are taken into account at all stages - from the early algorithmic design, via appropriate programming models, up to the final implementation.
The APPMM Workshop topics of interest include (but are not limited to) the following:
Novel programming models and associated frameworks, or extensions of existing programming models, to ease offloading and parallelization of computation to multi- and many-cores.
Compiler, runtime and parallelization approaches to optimally exploit specific features of heterogeneous hardware (e.g., hierarchical communication layout, NUMA, scratchpad memory, accelerators, etc.) and to maximize performance, energy and other relevant metrics in many-core operation.
Many-Core Architectures for emerging scientific computing applications
Architecture-assisted software design. Novel architectural concepts to boost software execution and to overcome scalability issues of current multi- and many-core systems. Hardware-assisted runtime environment services (e.g., synchronization, custom memory hierarchies, etc.)
Concepts for exploiting emerging vector extensions of instruction sets.
Many-core Hw/SW Design for Machine/Deep Learning processing and applications
Software engineering, code optimization, and code generation strategies for parallel systems with multi- and many-core processors.
Tools for performance and memory behavior analysis (including cache simulation) for parallel systems with multi- and many-core processors.
Performance modeling and performance engineering approaches for multi-thread and multi-process applications.
Application parallelization use cases, benchmarking and benchmark suites. Hardware-aware, compute- and memory-intensive simulations of real-world problems in computational science and engineering (for example, from applications in electrical, mechanical, civil, or medical engineering).
Manycore-aware approaches for large-scale parallel simulations in both implementation and algorithm design, including scalability studies.
INSTRUCTIONS FOR PAPER SUBMISSIONS